Multi-probe Interface Characterization of In0.65Ga0.35As/Al2O3 MOSFET

Through a combination of measurement techniques, we study the interface properties of In0.65Ga0.35As transistor with ALD deposited Al2O3 gate dielectric. We show that the interface trap density at In0.65Ga0.35As/Al2O3 interface can be relatively high, but the transistor still exhibits inversion characteristics. A detailed profiling of the interface traps shows that majority of the interface traps are donor-like, and explains the absence of Fermi level pinning in spite of the high interface trap density. Introduction With aggressive scaling of device dimensions, it is expected that the widely successful silicon CMOS technology will approach its fundamental limits within the next few technology nodes. Substrate material based on III-V compound semiconductor like InxGa1-xAs is an attractive choice for replacing silicon NMOS transistors due to their higher electron mobility [1-5]. However the interface properties of transistors based on III-V substrate materials are not well understood, and are often a topic of significant debate. In this paper we use a wide range of measurement techniques to characterize the In0.65Ga0.35As/Al2O3 interface so as to obtain the trap density, type and location in position and energy. We show that the interface trap densities are high, but remarkably/counter-intuitively, it is still possible to attain large inversion current since majority of the traps are donor-like. Interface trap characterization Fig. 1 shows the device structure used in the study, the fabrication steps of which are discussed in [1-2]. The IDVD characteristics of the device are shown in Fig. 2, and drain current exceeding 1A/mm is obtained. Capacitancevoltage (CV) measurements are carried out at various frequencies (Fig. 3) to study the interface properties of the transistor. The inversion capacitance increases at lower frequencies, suggesting the formation of inversion channel. The interface trap density (DIT) within the semiconductor bandgap is measured using the Hi-Lo CV method [6], and trap densities above 4.8x10/cm eV are obtained (see Fig. 9). Similar values of DIT in the order of 2-3x10/cm eV were also obtained using conductance (G-V) method [7]. Fig. 4a shows the transistor ID-VG characteristics. The sub-threshold slopes (SS) of the transistors are found to be high, indicating large interface trap density. Fig. 4b shows the SS and corresponding DIT which is in the order of 1-2x10/cm eV. It is interesting to note that although Figure 1. Device structure of InGaAs MOSFET used in the study. The fabrication steps are discussed in [1-2]. Figure 2. ID-VD characteristics of InGaAs MOSFET structure in Fig. 1. Drain current above 1A/mm is obtained with the In0.65Ga0.35As channel material. High drain current indicates formation of inversion channel. Figure 3. C-V characteristics measured at various frequencies with source/drain floating. CINV increases at lower frequencies suggesting channel inversion. The HF/LF CV curves are used to obtain DIT profile within the semiconductor bandgap. 500 nm 4x10/cm pIn0.53Ga0.47As 300 nm 1x10/cm pIn0.53Ga0.47As Gate Source Si implanted n region ALD high-k P InP Substrate 20 nm 1x10/cm p-In0.65Ga0.35As